Formal Verification based on Boolean Expression Diagrams

Boolean Expression Diagrams

Boolean Expression Diagrams

This paper presents a new data structure called Boolean Expression Diagrams (BEDs) for representing and manipulating Boolean functions. BEDs are a generalization of Binary Decision Diagrams (BDDs) which can represent any Boolean circuit in linear space and still maintain many of the desirable properties of BDDs. Two algorithms are described for transforming a BED into a reduced ordered BDD. One...

Integrating Boolean Verification with Formal Derivation

This summary describes results in integrating formal derivational reasoning with low level veri cation. The reported work is part of a project to construct an FPGA realization of Hunt's FM9001 Microprocessor description by applying the DDD (Digital Design Derivation) System in conjunction with low level veri cation systems. The purpose is to study the interaction between derivation and veri cat...

Design and formal verification of DZMBE+

In this paper, a new broadcast encryption scheme is presented based on threshold secret sharing and secure multiparty computation. This scheme is maintained to be dynamic in that a broadcaster can broadcast a message to any of the dynamic groups of users in the system and it is also fair in the sense that no cheater is able to gain an unfair advantage over other users. Another important feature...

Boolean Expression Diagrams ( Appears in LICS ' 97 )

This paper presents a new data structure called Boolean Expression Diagrams (BEDs) for representing and manipulating Boolean functions. BEDs are a generalization of Binary Decision Diagrams (BDDs) which can represent any Boolean circuit in linear space and still maintain many of the desirable properties of BDDs. Two algorithms are described for transforming a BED into a reduced ordered BDD. One...